Senior Design Engineer Networking
Oct 04, 2017San Jose, California
Senior Design Engineer - Networking (253464)
7 Months contract
San Jose, CA
Client, Inc. is a world leader in Memory, System LSI and LCD technologies. We are currently looking for exceptional Senior Design Engineer to join our team in San Jose, CA.
The Memory Solutions Lab (MSL) is part of Client’s Memory Business Unit, the industry's technology and volume leader in DRAM, NAND Flash, SRAM memory. MSL’s vision is to solve key problems & optimize architecture solutions for Cloud & Data center environments. We are an integral part of Client’s strong R&D focus & lab innovation engine. We work closely with development teams to bring feature innovation to product road maps.
We are currently looking for a Senior Design Engineer with expertise in Networking to join our team in San Jose, CA. The Candidate will be a key technical member of System Architecture Lab. He or she will join a team of experts in researching and developing innovative data center/ cloud networking, storage, and compute ASIC/ FPGA and system solutions. The ideal candidate must have prior experience developing architecture and design of leading edge networking, storage, embedded computing ASIC and/ or FPGA.
• Research architectural trade-offs of networked storage controller ASIC/ FPGA
• Research, evaluate and integrate acquired hardware Intellectual Property (IP)
• Develop new IP for high performance networked storage based solid state drives
• Research emerging technology standards and map to optimal implementation in FPGA/ ASIC
• Work with other hardware/ software architects developing one of a kind innovative FPGA prototypes, contribute to feasibility studies & developing solutions
• Assist software architects developing Linux/ Windows device driver, test and debug
• Propose and execute on innovations in software and hardware architecture based on their benefits to large-scale applications.
• B.S., M.S., or Ph.D. in Computer Engineering or Electrical Engineering
• At least 5 years of development experience and expertise in at least one of the following:
o Ethernet protocol accelerators such as TOE / UOE
o RDMA protocols such as InfiniBand, iWARP, RoCE v1/v2
o 10-100 Gb Ethernet controller, switch, or RNIC
• In depth background in HDL development, synthesis, debug, simulation, test bench creation and debug using CAD tools (Synopsys, Mentor, Cadence, or FPGA tools)
• Solid expertise in computer architecture, including experience with some of the following: server systems, data centers, processors, memory hierarchy, memory subsystems, storage, I/O and networking.
• Must be highly motivated with excellent verbal and written communication skills.
• Demonstrated attention to detail
• Ability to meet aggressive project deadlines in a team environment
• Ability to work successfully with cross-functional teams, including coordinating across organizational boundaries and geographies.
• Ability to create near term value within a strategic research environment.
• Comfortable working in a multinational environment and understands how to leverage cultural diversity
• Hands on lab prototype set up, testing, measurement and debug is highly desired.
• Understanding of low level software and device drivers such as Firmware, Boot, UEFI, PCIe, Ethernet controller and similar device drivers is desired.
• Understanding of typical hyper-scale and data center applications and benchmarks desired.